[IEEE 2002 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 2002)] 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizingTschanz, J.; Yibin Ye, ; Liqiong Wei, ; Govindarajulu, V.; Borkar, N.; Burns, S.; Karnik, T.; Borkar, S.; De, V. · 2002

[IEEE 2002 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 2002)] 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) techniqueYibin Ye, ; Khellah, M.; Somasekhar, D.; Farhang, A.; De, V. · 2002