[IEEE Workshop on VLSI Signal Processing - Los Angeles, CA (October 28-30, 1992)] Workshop on VLSI Signal Processing - A Systematic Folding Design Procedure For a1-D RLs Systolic Array
- 作者Lorenzelli, F.; Yao, K.
- 文件大小711.19KB
- 发表时间1992
- DOI10.1109/vlsisp.1992.641078
- 页码469-482
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