Computer Hardware Description Languages and their Applications || Verilog HDL Modeling Styles for Formal Verification
- 作者Balarin, Felice
- 文件大小654.44KB
- 发表时间1993
- DOI10.1016/b978-0-444-81641-2.50039-3
- 页码453-465
[IEEE 23rd Annual Symposium on Foundations of Computer Science - Chicago, IL, USA (1982.11.3-1982.11.5)] 23rd Annual Symposium on Foundations of Computer Science (sfcs 1982) - An efficient approximation scheme for the one-dimensional bin-packing problemKarmarkar, Narendra; Karmarkar, Narendra; Karmarkar, Narendra; Karmarkar, Narendra; Karp, Richard M.; Karp, Richard M.; Karp, Richard M.; Karp, Richard M. · 1982
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Assembly-Line Balancing-Dynamic Programming with Precedence ConstraintsMichael Held, Richard M. Karp and Richard Shareshian · Operations Research · 1963
ReplyCharles M. Epstein; Richard Stappenbeck; Herbert R. Karp · 1981
The complexity of parallel searchRichard M. Karp; Eli Upfal; Avi Wigderson · 1988
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