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A discrete syntax for level-sensitive latched circuits having n clocks and m phases

A discrete syntax for level-sensitive latched circuits having n clocks and m phases

Jennings, G.; Jennings, E.

作者Jennings, G.; Jennings, E.
卷第15卷
期第1期
文件大小2165.72KB
发表时间1996
DOI10.1109/43.486277
页码111-126

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