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[IEEE Comput. Soc 8th Great Lakes Symposium on VLSI - Lafayette, LA, USA (19-21 Feb. 1998)] Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222) - A design-for-testability technique for detecting delay faults in logic circuits

[IEEE Comput. Soc 8th Great Lakes Symposium on VLSI - Lafayette, LA, USA (19-21 Feb. 1998)] Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222) - A design-for-testability technique for detecting delay faults in logic circuits

Raahemifar, K.; Ahmadi, M.

作者Raahemifar, K.; Ahmadi, M.
文件大小159.88KB
发表时间1998
DOI10.1109/glsv.1998.665244
页码249-255

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