[IEEE Comput. Soc 14th Symposium on Computer Arithmetic - Adelaide, SA, Australia (14-16 April 1999)] Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) - Reduced latency IEEE floating-point standard adder architectures
Beaumont-Smith, A.; Burgess, N.; Lefrere, S.; Lim, C.C.
- 作者Beaumont-Smith, A.; Burgess, N.; Lefrere, S.; Lim, C.C.
- 文件大小141.36KB
- 发表时间1999
- DOI10.1109/arith.1999.762826
- 页码35-42