[IEEE International Electron Devices Meeting 1999. Technical Digest - Washington, DC, USA (5-8 Dec. 1999)] International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) - An embedded 0.405 μm/sup 2/ stacked DRAM technology integrated with high-performance 0.2 μm CMOS logic and 6-level metalization
- 作者Yoshida, M.; Asaka, K.; Hoshino, Y.; Sugawara, Y.; Aoki, H.; Saito, M.; Imai, A.; Enomoto, H.; Kawakami, H.; Furukawa, R.; Fukuda, N.; Tsuneno, K.; Maeda, F.; Kogayu, H.; Ishikawa, I.; Ogaya, K.; Takakura, T.
- 文件大小397.66KB
- 发表时间1999
- DOI10.1109/iedm.1999.823842
- 页码41-44
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