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[IEEE Comput. Soc 18th IEEE VLSI Test Symposium - Montreal, Que., Canada (30 April-4 May 2000)] Proceedings 18th IEEE VLSI Test Symposium - Detectability conditions for interconnection open defects

[IEEE Comput. Soc 18th IEEE VLSI Test Symposium - Montreal, Que., Canada (30 April-4 May 2000)] Proceedings 18th IEEE VLSI Test Symposium - Detectability conditions for interconnection open defects

Champac, V.H.; Zenteno, A.
  • 作者Champac, V.H.; Zenteno, A.
  • 文件大小222.44KB
  • 发表时间2000
  • DOI10.1109/VTEST.2000.843859
  • 页码305-311
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