Delay fault testing of IP-based designs via symbolic path modeling

• 期刊名称IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• 作者Hyungwon Kim, ; Hayes, J.P.
• 卷第9卷
• 期第5期
• 印刷ISSN1063-8210
• 电子ISSN1557-9999
• 文件大小767.02KB
• 发表时间2001-10
• DOI10.1109/92.953500
• 页码661-678