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[IEEE Comput. Soc 2001 IEEE International Workshop on Memory Technology, Design and Testing - San Jose, CA, USA (6-7 Aug. 2001)] Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing - An approach for evaluation of redundancy analysis algorithms

[IEEE Comput. Soc 2001 IEEE International Workshop on Memory Technology, Design and Testing - San Jose, CA, USA (6-7 Aug. 2001)] Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing - An approach for evaluation of redundancy analysis algorithms

Shoukourian, S.; Vardanian, V.; Zorian, Y.

作者Shoukourian, S.; Vardanian, V.; Zorian, Y.
文件大小361.89KB
发表时间2001
DOI10.1109/mtdt.2001.945228
页码51-55

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