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[IEEE Comput. Soc 20th IEEE VLSI Test Symposium (VTS 2002) - Monterey, CA, USA (28 April-2 May 2002)] Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) - On using rectangle packing for SOC wrapper/TAM co-optimization

[IEEE Comput. Soc 20th IEEE VLSI Test Symposium (VTS 2002) - Monterey, CA, USA (28 April-2 May 2002)] Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) - On using rectangle packing for SOC wrapper/TAM co-optimization

Iyengar, V.; Chakrabarty, K.; Marinissen, E.J.

作者Iyengar, V.; Chakrabarty, K.; Marinissen, E.J.
文件大小379.54KB
发表时间2002
DOI10.1109/VTS.2002.1011146
页码253-258

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