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[IEEE Comput. Soc 2002 3rd International Symposium on Quality Electronic Design - San Jose, CA, USA (18-21 March 2002)] Proceedings International Symposium on Quality Electronic Design - Synthesis of selectively clocked skewed logic circuits

[IEEE Comput. Soc 2002 3rd International Symposium on Quality Electronic Design - San Jose, CA, USA (18-21 March 2002)] Proceedings International Symposium on Quality Electronic Design - Synthesis of selectively clocked skewed logic circuits

Aiqun Cao, ; Sirisantana, N.; Cheng-Kok Koh, ; Roy, K.

作者Aiqun Cao, ; Sirisantana, N.; Cheng-Kok Koh, ; Roy, K.
文件大小391.94KB
发表时间2002
DOI10.1109/isqed.2002.996737
页码229-234

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