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Design of squarers modulo A with low-level pipelining

Design of squarers modulo A with low-level pipelining

Piestrak, S.J.

期刊名称IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
作者Piestrak, S.J.
卷第49卷
期第1期
印刷ISSN1057-7130
文件大小414.71KB
发表时间2002
DOI10.1109/82.996056

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