[IEEE Comput. Soc 16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India (4-8 Jan. 2003)] 16th International Conference on VLSI Design, 2003. Proceedings. - Optimization of 1.8V I/O circuits for performance, reliability at the 100 nm technology node
Menezes, V.; Keshav, C.B.; Gupta, S.; Roopashree, M.; Krishnan, S.; Amerasekera, A.; Palau, G.
- 作者Menezes, V.; Keshav, C.B.; Gupta, S.; Roopashree, M.; Krishnan, S.; Amerasekera, A.; Palau, G.
- 文件大小391.97KB
- 发表时间2003
- DOI10.1109/ICVD.2003.1183125
- 页码122-127