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Novel on-chip circuit for jitter testing in high-speed PLLs

Novel on-chip circuit for jitter testing in high-speed PLLs

Cazeaux, J.M.; Omana, M.; Metra, C.

作者Cazeaux, J.M.; Omana, M.; Metra, C.
卷第54卷
期第5期
印刷ISSN0018-9456
电子ISSN1557-9662
文件大小441.84KB
发表时间2005
DOI10.1109/tim.2005.855104
页码1779-1788

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