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Low-power scan design using first-level supply gating

Low-power scan design using first-level supply gating

Bhunia, S.; Mahmoodi, H.; Ghosh, D.; Mukhopadhyay, S.; Roy, K.

期刊名称IEEE Transactions on Very Large Scale Integration (VLSI) Systems
作者Bhunia, S.; Mahmoodi, H.; Ghosh, D.; Mukhopadhyay, S.; Roy, K.
卷第13卷
期第3期
印刷ISSN1063-8210
电子ISSN1557-9999
文件大小717.41KB
发表时间2005-03
DOI10.1109/tvlsi.2004.842885
页码384-395

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