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[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Kyoto, Japan (June 14-16, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Issues and optimization of millisecond anneal process for 45 nm node and beyond

[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Kyoto, Japan (June 14-16, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Issues and optimization of millisecond anneal process for 45 nm node and beyond

Adachi, K.; Ohuchi, K.; Aoki, N.; Tsujii, H.; Ito, T.; Itokawa, H.; Matsuo, K.; Suguro, K.; Honguh, Y.; Tamaoki, N.; Ishimaru, K.; Ishiuchi, H.
  • 作者Adachi, K.; Ohuchi, K.; Aoki, N.; Tsujii, H.; Ito, T.; Itokawa, H.; Matsuo, K.; Suguro, K.; Honguh, Y.; Tamaoki, N.; Ishimaru, K.; Ishiuchi, H.
  • 文件大小540.48KB
  • 发表时间2005
  • DOI10.1109/.2005.1469245
  • 页码142-143
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