[IEEE 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. - Honolulu, HI, USA (June 13-15, 2006)] 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. - Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-Implantation for Sub-30-nm Strained CMOS Devices

• 作者Yamamoto, T.; Kubo, T.; Sukegawa, T.; Hashimoto, K.; Kase, M.
• 文件大小565.32KB
• 发表时间2006
• DOI10.1109/VLSIT.2006.1705279
• 页码186-187