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FSM-Based Digital Design Using Verilog HDL (Minns/FSM-Based Digital Design Using Verilog HDL) || Asynchronous Finite-State Machines

FSM-Based Digital Design Using Verilog HDL (Minns/FSM-Based Digital Design Using Verilog HDL) || Asynchronous Finite-State Machines

Minns, Peter; Elliott, Ian

作者Minns, Peter; Elliott, Ian
文件大小374.26KB
发表时间2008
DOI10.1002/9780470987629.ch9
页码267-312

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