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Theoretical analysis of the vertical LOCOS DMOS transistor with process-induced stress enhancement

Theoretical analysis of the vertical LOCOS DMOS transistor with process-induced stress enhancement

S. Reggiani; M. Denison; E. Gnani; A. Gnudi; G. Baccarani; S. Pendharkar; R. Wise
  • 作者S. Reggiani; M. Denison; E. Gnani; A. Gnudi; G. Baccarani; S. Pendharkar; R. Wise
  • 卷第54卷
  • 期第9期
  • 印刷ISSN0038-1101
  • 文件大小1027.94KB
  • 发表时间2010
  • DOI10.1016/j.sse.2010.04.014
  • 页码950-956
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