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Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits

Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits

Sathanur, Ashoka; Benini, Luca; Macii, Alberto; Macii, Enrico; Poncino, Massimo
  • 期刊名称IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 作者Sathanur, Ashoka; Benini, Luca; Macii, Alberto; Macii, Enrico; Poncino, Massimo
  • 卷第19卷
  • 期第3期
  • 印刷ISSN1063-8210
  • 电子ISSN1557-9999
  • 文件大小1287.26KB
  • 发表时间2011-03
  • DOI10.1109/tvlsi.2009.2035448
  • 页码469-482
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