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[IEEE 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012 - Seoul, Korea (South) (2012.05.20-2012.05.23)] 2012 IEEE International Symposium on Circuits and Systems - A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

[IEEE 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012 - Seoul, Korea (South) (2012.05.20-2012.05.23)] 2012 IEEE International Symposium on Circuits and Systems - A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

Lu, Ping; Wu, Ying; Andreani, Pietro
  • 作者Lu, Ping; Wu, Ying; Andreani, Pietro
  • 文件大小695.85KB
  • 发表时间2012
  • DOI10.1109/iscas.2012.6271835
  • 页码2593-2596
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