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[IEEE 2012 IEEE/CPMT 28th Semiconductor Thermal Measurement & Management Symposium (SEMI-THERM) - San Jose, CA, USA (2012.03.18-2012.03.22)] 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM) - Cache leakage power estimation using architectural model for 32 nm and 16 nm technology nodes

[IEEE 2012 IEEE/CPMT 28th Semiconductor Thermal Measurement & Management Symposium (SEMI-THERM) - San Jose, CA, USA (2012.03.18-2012.03.22)] 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM) - Cache leakage power estimation using architectural model for 32 nm and 16 nm technology nodes

Zajac, Piotr; Janicki, Marcin; Szermer, Michal; Maj, Cezary; Pietrzak, Piotr; Napieralski, Andrzej
  • 作者Zajac, Piotr; Janicki, Marcin; Szermer, Michal; Maj, Cezary; Pietrzak, Piotr; Napieralski, Andrzej
  • 文件大小244.60KB
  • 发表时间2012
  • DOI10.1109/STHERM.2012.6188865
  • 页码308-312
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