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[IEEE 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Austin, TX, USA (2012.10.3-2012.10.5)] 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

[IEEE 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Austin, TX, USA (2012.10.3-2012.10.5)] 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Bolchini, C.; Miele, A.; Sandionigi, C.; Ottavi, M.; Pontarelli, S.; Salsano, A.; Metra, C.; Omana, M.; Rossi, D.; Reorda, M. Sonza; Sterpone, L.; Violante, M.; Gerardin, S.; Bagatin, M.; Paccagnella, A.
  • 作者Bolchini, C.; Miele, A.; Sandionigi, C.; Ottavi, M.; Pontarelli, S.; Salsano, A.; Metra, C.; Omana, M.; Rossi, D.; Reorda, M. Sonza; Sterpone, L.; Violante, M.; Gerardin, S.; Bagatin, M.; Paccagnella, A.
  • 文件大小130.19KB
  • 发表时间2012
  • DOI10.1109/dft.2012.6378211
  • 页码121-125
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