[IEEE 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Karlsruhe, Germany (2013.09.9-2013.09.11)] 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design
- 作者Urdahl, Joakim; Udupi, Shrinidhi; Stoffel, Dominik; Kunz, Wolfgang
- 文件大小261.32KB
- 发表时间2013
- DOI10.1109/PATMOS.2013.6662157
- 页码67-74
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