A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

Plouchart, J.-O.; Ferriss, M.; Natarajan, A. S.; Valdes-Garcia, A.; Sadhu, B.; Rylyakov, A.; Parker, B. D.; Beakes, M.; Babakhani, A.; Yaldiz, S.; Pileggi, L.; Harjani, R.; Reynolds, S.; Tierno, J. A.; Friedman, D.

期刊名称IEEE Transactions on Circuits and Systems I: Regular Papers
作者Plouchart, J.-O.; Ferriss, M.; Natarajan, A. S.; Valdes-Garcia, A.; Sadhu, B.; Rylyakov, A.; Parker, B. D.; Beakes, M.; Babakhani, A.; Yaldiz, S.; Pileggi, L.; Harjani, R.; Reynolds, S.; Tierno, J. A.; Friedman, D.
卷第60卷
期第8期
印刷ISSN1549-8328
电子ISSN1558-0806
文件大小2251.00KB
发表时间2013-08
DOI10.1109/TCSI.2013.2265961
页码2009-2017

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A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS