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Trading off circuit lines and gate costs in the synthesis of reversible logic

Trading off circuit lines and gate costs in the synthesis of reversible logic

Wille, Robert; Soeken, Mathias; Michael Miller, D.; Drechsler, Rolf

期刊名称Integration, the VLSI Journal
作者Wille, Robert; Soeken, Mathias; Michael Miller, D.; Drechsler, Rolf
卷第47卷
期第2期
印刷ISSN0167-9260
文件大小1054.87KB
发表时间2014-03
DOI10.1016/j.vlsi.2013.08.002
页码284-294

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