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[IEEE 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Warsaw, Poland (2014.4.23-2014.4.25)] 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

[IEEE 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Warsaw, Poland (2014.4.23-2014.4.25)] 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

Jordans, Roel; Diken, Erkan; Jozwiak, Lech; Corporaal, Henk
  • 作者Jordans, Roel; Diken, Erkan; Jozwiak, Lech; Corporaal, Henk
  • 文件大小120.68KB
  • 发表时间2014
  • DOI10.1109/ddecs.2014.6868768
  • 页码83-88
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