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[IEEE 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Amsterdam, Netherlands (2014.10.1-2014.10.3)] 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Shortest path reduction in a class of uniform fault tolerant networks

[IEEE 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Amsterdam, Netherlands (2014.10.1-2014.10.3)] 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Shortest path reduction in a class of uniform fault tolerant networks

Joshi, Prashant D.; Hamdioui, Said
  • 作者Joshi, Prashant D.; Hamdioui, Said
  • 文件大小4315.88KB
  • 发表时间2014
  • DOI10.1109/dft.2014.6962102
  • 页码234-239
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