Floorplan-aware analog IC sizing and optimization based on topological constraints

• 期刊名称Integration, the VLSI Journal
• 作者Lourenço, Nuno; Canelas, António; Póvoa, Ricardo; Martins, Ricardo; Horta, Nuno
• 卷第48卷
• 印刷ISSN0167-9260
• 文件大小7390.49KB
• 发表时间2015-01
• DOI10.1016/j.vlsi.2014.07.002
• 页码183-197