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Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

J. Yoon; E. Jeong; C. Baek; Y. Kim; J. Hong; J. Lee; R. Baek; Y. Jeong
  • 作者J. Yoon; E. Jeong; C. Baek; Y. Kim; J. Hong; J. Lee; R. Baek; Y. Jeong
  • 文件大小1319.77KB
  • 发表时间2015
  • DOI10.1109/LED.2015.2464706
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