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AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Lourenço, Nuno; Martins, Ricardo; Canelas, António; Póvoa, Ricardo; Horta, Nuno

期刊名称Integration, the VLSI Journal
作者Lourenço, Nuno; Martins, Ricardo; Canelas, António; Póvoa, Ricardo; Horta, Nuno
印刷ISSN0167-9260
文件大小6342.66KB
发表时间2016-5
DOI10.1016/j.vlsi.2016.04.009

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