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Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control

Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control

Qiu, Mo; Yu, Simin; Wen, Yuqiong; Lü, Jinhu; He, Jianbin; Lin, Zhuosheng
  • 期刊名称International Journal of Bifurcation and Chaos
  • 作者Qiu, Mo; Yu, Simin; Wen, Yuqiong; Lü, Jinhu; He, Jianbin; Lin, Zhuosheng
  • 卷第27卷
  • 期第3期
  • 印刷ISSN0218-1274
  • 电子ISSN1793-6551
  • 文件大小831.41KB
  • 发表时间2017-03
  • DOI10.1142/S0218127417500407
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