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[IEEE 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Dresden, Germany (2018.3.19-2018.3.23)] 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells

[IEEE 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Dresden, Germany (2018.3.19-2018.3.23)] 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells

Heittmann, Arne; Noll, Tobias G.
  • 作者Heittmann, Arne; Noll, Tobias G.
  • 文件大小166.87KB
  • 发表时间2018
  • DOI10.23919/DATE.2018.8342250
  • 页码1496-1499
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