Comparing layouts with HDL models: a formal verification techniqueKam, T.; Subrahmanyam, P.A. · 1995

[IEEE Comput. Soc. Press 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA (11-14 Oct. 1992)] Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Comparing layouts with HDL models: a formal verification techniqueKam, T.; Subrahmanyam, P.A. · 1992