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[IEEE IEEE 1995 Custom Integrated Circuits Conference - Santa Clara, CA, USA (1-4 May 1995)] Proceedings of the IEEE 1995 Custom Integrated Circuits Conference - Leading-zero anticipatory logic for high-speed floating point addition

[IEEE IEEE 1995 Custom Integrated Circuits Conference - Santa Clara, CA, USA (1-4 May 1995)] Proceedings of the IEEE 1995 Custom Integrated Circuits Conference - Leading-zero anticipatory logic for high-speed floating point addition

Suzuki, H.; Nakase, Y.; Makino, H.; Morinaka, H.; Mashiko, K.

作者Suzuki, H.; Nakase, Y.; Makino, H.; Morinaka, H.; Mashiko, K.
文件大小457.37KB
发表时间1995
DOI10.1109/cicc.1995.518253
页码589-592

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