Skewed CMOS: noise-tolerant high-performance low-power static circuit familySolomatnikov, A.; Somasekhar, D.; Sirisantana, N.; Roy, K. · 2002

[IEEE Comput. Soc 2002 3rd International Symposium on Quality Electronic Design - San Jose, CA, USA (18-21 March 2002)] Proceedings International Symposium on Quality Electronic Design - Synthesis of selectively clocked skewed logic circuitsAiqun Cao, ; Sirisantana, N.; Cheng-Kok Koh, ; Roy, K. · 2002

[IEEE Conference of Asia and South Pacific Design Automation 2003 - Kitakyushu, Japan (21-24 Jan. 2003)] Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003. - Integer linear programming-based synthesis of skewed logic circuitsAiqun Cao, ; Sirisantana, N.; Cheng-Kok Koh, ; Roy, K. · 2003

[IEEE ESSCIRC 2004 - 29th European Solid-State Circuits Conference - Estoril, Portugal (16-18 Sept. 2003)] ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705) - A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologiesSirisantana, N.; Roy, K. · 2003

[IEEE Comput. Soc 2000 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2000 - Austin, TX, USA (17-20 Sept. 2000)] Proceedings 2000 International Conference on Computer Design - High-performance low-power CMOS circuits using multiple channel length and multiple oxide thicknessSirisantana, N.; Wei, L.; Roy, K. · 2000

[ACM ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design - Huntington Beach, CA, USA (6-7 Aug. 2001)] ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) - Selectively clocked skewed logic (SCSL): a robust low-power logic style for high-performance applicationsSirisantana, N.; Cao, A.; Davidson, S.; Cheng-Kok Koh, ; Roy, K. · 2001