[IEEE Comput. Soc Eighth IEEE International High-Level Design Validation and Test Workshop - San Francisco, CA, USA (12-14 Nov. 2003)] Eighth IEEE International High-Level Design Validation and Test Workshop - Verifying LOC based functional and performance constraints
- 作者Xi Chen, ; Hsieh, H.; Balarin, F.; Watanabe, Y.
- 文件大小475.85KB
- 发表时间2003
- DOI10.1109/HLDVT.2003.1252479
- 页码83-88
Logic of constraints: a quantitative performance and functional constraint formalismXi Chen; Hsieh, H.; Balarin, F.; Watanabe, Y. · 2004
[IEEE 2003. Design Automation Conference - Anaheim, CA, USA (2-6 June 2003)] Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) - Automatic trace analysis for logic of constraintsXi Chen, ; Hsieh, H.; Balarin, F.; Watanabe, Y. · 2003
[IEEE Comput. Soc IEEE International High Level Design Validation and Test Workshop (HLDVT'02) - Cannes, France (27-29 Oct. 2002)] Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. - Formal verification of embedded system designs at multiple levels of abstractionXi Chen, ; Fang Chen, ; Hsieh, H.; Balarin, F.; Watanabe, Y. · 2002
[IEEE Comput. Soc International Conference on Application of Concurrency to System Design (ACSD'2003) - Guimaraes, Portugal (18-20 June 2003)] Third International Conference on Application of Concurrency to System Design, 2003. Proceedings. - Case studies of model checking for embedded system designsXi Chen, ; Hsieh, H.; Balarin, F.; Watanabe, Y. · 2003
[IEEE Comput. Soc 6th Design Automation and Test in Europe (DATE 03) - Munich, Germany (3-7 March 2003)] 2003 Design, Automation and Test in Europe Conference and Exhibition - Automatic generation of simulation monitors from quantitative constraint formula [system-level verification]Xi Chen, ; Hsieh, H.; Balarin, F.; Watanabe, Y. · 2003