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<![CDATA[Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design]]>Alioto, Massimo; Consoli, Elio; Palumbo, Gaetano · 2010
Flip-Flop Design in Nanometer CMOS ||Alioto, Massimo; Consoli, Elio; Palumbo, Gaetano · 2015
From energy-delay metrics to constraints on the design of digital circuitsMassimo Alioto; Elio Consoli; Gaetano Palumbo · 2012
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay SpaceAlioto, Massimo; Consoli, Elio; Palumbo, Gaetano · IEEE Transactions on Circuits and Systems I: Regular Papers · 2010
Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on TimingAlioto, Massimo; Consoli, Elio; Palumbo, Gaetano · IEEE Transactions on Circuits and Systems I: Regular Papers · 2015
Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed LatchesConsoli, Elio; Palumbo, Gaetano; Rabaey, Jan M.; Alioto, Massimo · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOSConsoli, Elio; Alioto, Massimo; Palumbo, Gaetano; Rabaey, Jan
Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of VariationsAlioto, Massimo; Consoli, Elio; Palumbo, Gaetano · IEEE Transactions on Circuits and Systems I: Regular Papers · 2015