Power-/energy-efficient BIST schemes for processor data pathsKranitis, N.; Gizopoulos, D.; Paschalis, A.; Psarakis, M.; Zorian, Y. · IEEE Design & Test of Computers · 2000

An effective built-in self-test scheme for parallel multipliersGizopoulos, D.; Paschalis, A.; Zorian, Y. · 1999

Sequential fault modeling and test pattern generation for CMOS iterative logic arraysPsarakis, M.; Gizopoulos, D.; Paschalis, A.; Zorian, Y. · 2000

Low-cost software-based self-testing of RISC processor coresKranitis, N.; Xenoulis, G.; Gizopoulos, D.; Paschalis, A.; Zorian, Y. · 2003

[ACM Press the conference - Munich, Germany (1999..-..)] Proceedings of the conference on Design, automation and test in Europe - DATE '99 - An effective BIST architecture for fast multiplier coresPaschalis, A.; Gizopoulos, D.; Kranitis, N.; Psarakis, M.; Zorian, Y. · 1999

[Int. Test Conference 1995 IEEE International Test Conference (ITC) - Washington, DC, USA (21-25 Oct. 1995)] Proceedings of 1995 IEEE International Test Conference (ITC) - An effective BIST scheme for Booth multipliersGizopoulos, D.; Paschalis, A.; Zorian, Y. · 1995

[IEEE Comput. Soc 18th IEEE VLSI Test Symposium - Montreal, Que., Canada (30 April-4 May 2000)] Proceedings 18th IEEE VLSI Test Symposium - Low power/energy BIST scheme for datapathsGizopoulos, D.; Krantitis, N.; Paschalis, A.; Psarakis, M.; Zorian, Y. · 2000

[ACM Press the conference - Paris, France (2000.03.27-2000.03.30)] Proceedings of the conference on Design, automation and test in Europe - DATE '00 - Effective low power BIST for datapaths (poster paper)Gizopoulos, D.; Kranitis, N.; Paschalis, A.; Psarakis, M.; Zorian, Y. · 2000