![[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Kyoto, Japan (June 14-16, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Issues and optimization of millisecond anneal process for 45 nm node and beyond]()
[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Kyoto, Japan (June 14-16, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Issues and optimization of millisecond anneal process for 45 nm node and beyondAdachi, K.; Ohuchi, K.; Aoki, N.; Tsujii, H.; Ito, T.; Itokawa, H.; Matsuo, K.; Suguro, K.; Honguh, Y.; Tamaoki, N.; Ishimaru, K.; Ishiuchi, H. · 2005