Delay Modeling and Statistical Design of Pipelined Circuit Under Process VariationDatta, A.; Bhunia, S.; Mukhopadhyay, S.; Roy, K. · 2006

Low-power scan design using first-level supply gatingBhunia, S.; Mahmoodi, H.; Ghosh, D.; Mukhopadhyay, S.; Roy, K. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2005

Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuitsMukhopadhyay, S.; Bhunia, S.; Roy, K. · 2006

[IEEE 14th Asian Test Symposium (ATS'05) - Calcutta, India (2005.12.21-2005.12.21)] 14th Asian Test Symposium (ATS'05) - A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter VariationsDatta, A.; Bhunia, S.; Mukhopadhyay, S.; Roy, K. · 2005

[IEEE Asia and South Pacific Conference on Design Automation, 2006. - Yokohama, Japan (Jan. 24, 2006)] Asia and South Pacific Conference on Design Automation, 2006. - Speed binning aware design methodology to improve profit under parameter variationsDatta, A.; Bhunia, S.; Jung Hwan Choi, ; Mukhopadhyay, S.; Roy, K. · 2006

[IEEE Design, Automation and Test in Europe - Munich, Germany (07-11 March 2005)] Design, Automation and Test in Europe - Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm TechnologiesDatta, A.; Bhunia, S.; Mukhopadhyay, S.; Banerjee, N.; Roy, K. · 2005

[IEEE 11th IEEE International On-Line Testing Symposium - French Riviera, France (2005.07.8-2005.07.8)] 11th IEEE International On-Line Testing Symposium - Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm TechnologyDatta, A.; Mukhopadhyay, S.; Bhunia, S.; Roy, K. · 2005