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[IEEE 2012 IEEE International Test Conference (ITC) - Anaheim, CA, USA (2012.11.5-2012.11.8)] 2012 IEEE International Test Conference - Hybrid selector for high-X scan compressionWohl, P.; Waicukauski, J. A.; Neuveux, F.; Colburn, J. E. · 2012
[Int. Test Conference International Test Conference 1997 - Washington, DC, USA (1-6 Nov. 1997)] Proceedings International Test Conference 1997 - A unified interface for scan test generation based on STILWohl, P.; Waicukauski, J. · 1997
[IEEE 2013 IEEE 31st VLSI Test Symposium (VTS) - Berkeley, CA (2013.4.29-2013.5.2)] 2013 IEEE 31st VLSI Test Symposium (VTS) - Improving test generation by use of majority gatesWohl, P.; Waicukauski, J. A. · 2013
[Int. Test. Conference IEEE Computer Society International Test Conference (ICSM'99) - Atlantic City, NJ, USA (28-30 Sept. 1999)] International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) - Using Verilog simulation libraries for ATPGWohl, P.; Waicukauski, J. · 1999
[Int. Test Conference International Test Conference 2000 - Atlantic City, NJ, USA (3-5 Oct. 2000)] Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) - Optimizing the flattened test-generation model for very large designsWohl, P.; Waicukauski, J. · 2000
[Int. Test Conference International Test Conference 1996. Test and Design Validity - Washington, DC, USA (20-25 Oct. 1996)] Proceedings International Test Conference 1996. Test and Design Validity - Test generation for ultra-large circuits using ATPG constraints and test-pattern templatesWohl, P.; Waicukauski, J. · 1996
[IEEE Comput. Soc. Press Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) - Monterey, CA, USA (27 April-1 May 1997)] Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) - Using ATPG for clock rules checking in complex scan designsWohl, P.; Waicukauski, J. · 1997